Study and fabrication of MOSFET with III-V materials

Le système autonome nécessite une consommation d'énergie inférieur à 100μW pour qu’ils puissent récupérer l’énergie environnementale. Le transistor MOSFET, étant le composé principal de ce système, peut permettre cela en améliorant ces performances. Le matériaux III-V présente un intérêt à être appliqué au transistor MOSFET en considérant ses propres propriétés tel la haute vitesse thermique d’électron, la haute vitesse de saturation, la faible bande interdite. D'aussi hautes performances de transistor avec de basse consommation d'énergie peut être envisagé grâce au MOSFET III-V. Des technologies de fabrication de MOSFET In0.53Ga0.47As ont été développées avec ces mesures statiques et dynamiques. Un IdMAX=180mA/mm, gmMAX=110mS/mm, fT=150GHz, et fMAX=47GHz ont été obtenus pour un transistor de longueur de grille de 50nm. Différentes voies d’amélioration ont été étudiées y compris le procédé gate-last comparé au gate-first, l’effet PDA, et l’effet PPA. Le procédé gate-last démontre moins de dégradation de l’oxyde avec de meilleures performances que gate-first. PDA n’a pas d'effet important sur les performances du transistor. PPA a démontré un effet de passivation de certains défauts dans l’oxyde et dans l’interface. Des structures alternatives ont été étudiées comme la structure MOSHEMT de maille adapté et pseudomorphique, montrant de meilleures performances avec une IdMAX=300mA/mm, gmMAX=200mS/mm, fT=200GHz et fMAX=50GHz pour un transistor de longueur de grille de 100nm. Ces performances DC sont loin de l’état de l’art, tandis que les performances RF sont parmi les meilleures. La perspective de ce travail est d’améliorer la qualité d’oxyde en baissant le budget thermique et aussi d'utilier de prometteuses strucutres comme MOS-COMB (la structure MOS-Thin body avec couche barrière entre l’oxyde et le semiconducteur). La structure MOSFET InAs de haute performance pourrait aussi être envisagé en réduisant le budget thermique au cours de la fabrication.The autonomous system requires a power consumption of less than 100μW so that they can recover energy from the environment. MOSFET, being a major component of this system can achieve this low power consumption requirement by improving its performance. III-V materials are of interest to be applied to MOSFET considering its own properties such as high electron thermal mobility, high saturation velocity, and low band gap. So high-performance transistor with low power consumption can be expected by III-V MOSFETs. Fabrication technologies of In0.53Ga0.47As MOSFETs have been developed with its static and dynamic measurements. An IdMAX=180mA/mm, gmMAX=110mS/mm, fT=150GHz and fMAX=47GHz were obtained for a transistor gate length of 50nm. Different ways of improvement were studied including the gate-last process compared with gate-first, the PDA effect, and the PPP effect. The gate-last process shows less degradation of the oxide with better performance than gate-first. PDA has no prominent effect on the performance of transistor. PPA has been shown to have a passivation effect of certain defects in the oxide and interface. Alternative structures have been studied such as the structure MOSHEMT with lattice matched and pseudomorphic, showing best performances like IdMAX=300mA/mm, gmMAX=200mS/mm, fT=200GHz and fMAX=50GHz for a transistor gate length of 100nm. DC performance is far from the state of the art, while the RF performances are among the best. The perspective of this work is to improve the oxide quality by lowering the thermal budget and also to use promising structures as MOS-COMB (MOS-Thin body structure with barrier layer between the oxide and semiconductor). The MOSFET InAs with high-performance could also be expected by reducing the thermal budget during the fabrication

Characterization of border traps in III-V MOSFETs using an RF transconductance method

The significant defect-induced increase in transconductance at high frequencies in some III-V MOSFETs is utilized to reveal the spatial distribution and energy profile of traps in the gate dielectric. The frequency response of the border traps is modeled as a distributed RC network inserted in the small signal model. Surface-channel InGaAs MOSFETs with Al2O3/HfO2 high-k gate dielectric are evaluated; especially the effects of inserting an InP cap layer in the gate stack

Total Ionizing Dose Effects of Si Vertical Diffused MOSFET with SiO2 and Si3N4/SiO2 Gate Dielectrics

The total ionizing dose irradiation effects are investigated in Si vertical diffused MOSFETs (VDMOSs) with different gate dielectrics including single SiO2 layer and double Si3N4/SiO2 layer. Radiation-induced holes trapping is greater for single SiO2 layer than for double Si3N4/SiO2 layer. Dielectric oxidation temperature dependent TID effects are also studied. Holes trapping induced negative threshold voltage shift is smaller for SiO2 at lower oxidation temperature. Gate bias during irradiation leads to different VTH shift for different gate dielectrics. Single SiO2 layer shows the worst negative VTH at VG=0 V, while double Si3N4/SiO2 shows negative VTH shift at VG=-5 V, positive VTH shift at VG=10 V, and negligible VTH shift at VG=0 V

Etude et fabrication de MOSFET de la filière III-V

Le système autonome nécessite une consommation d'énergie inférieur à 100 W pour qu ils puissent récupérer l énergie environnementale. Le transistor MOSFET, étant le composé principal de ce système, peut permettre cela en améliorant ces performances. Le matériaux III-V présente un intérêt à être appliqué au transistor MOSFET en considérant ses propres propriétés tel la haute vitesse thermique d électron, la haute vitesse de saturation, la faible bande interdite. D'aussi hautes performances de transistor avec de basse consommation d'énergie peut être envisagé grâce au MOSFET III-V. Des technologies de fabrication de MOSFET In0.53Ga0.47As ont été développées avec ces mesures statiques et dynamiques. Un IdMAX=180mA/mm, gmMAX=110mS/mm, fT=150GHz, et fMAX=47GHz ont été obtenus pour un transistor de longueur de grille de 50nm. Différentes voies d amélioration ont été étudiées y compris le procédé gate-last comparé au gate-first, l effet PDA, et l effet PPA. Le procédé gate-last démontre moins de dégradation de l oxyde avec de meilleures performances que gate-first. PDA n a pas d'effet important sur les performances du transistor. PPA a démontré un effet de passivation de certains défauts dans l oxyde et dans l interface. Des structures alternatives ont été étudiées comme la structure MOSHEMT de maille adapté et pseudomorphique, montrant de meilleures performances avec une IdMAX=300mA/mm, gmMAX=200mS/mm, fT=200GHz et fMAX=50GHz pour un transistor de longueur de grille de 100nm. Ces performances DC sont loin de l état de l art, tandis que les performances RF sont parmi les meilleures. La perspective de ce travail est d améliorer la qualité d oxyde en baissant le budget thermique et aussi d'utilier de prometteuses strucutres comme MOS-COMB (la structure MOS-Thin body avec couche barrière entre l oxyde et le semiconducteur). La structure MOSFET InAs de haute performance pourrait aussi être envisagé en réduisant le budget thermique au cours de la fabrication.The autonomous system requires a power consumption of less than 100 W so that they can recover energy from the environment. MOSFET, being a major component of this system can achieve this low power consumption requirement by improving its performance. III-V materials are of interest to be applied to MOSFET considering its own properties such as high electron thermal mobility, high saturation velocity, and low band gap. So high-performance transistor with low power consumption can be expected by III-V MOSFETs. Fabrication technologies of In0.53Ga0.47As MOSFETs have been developed with its static and dynamic measurements. An IdMAX=180mA/mm, gmMAX=110mS/mm, fT=150GHz and fMAX=47GHz were obtained for a transistor gate length of 50nm. Different ways of improvement were studied including the gate-last process compared with gate-first, the PDA effect, and the PPP effect. The gate-last process shows less degradation of the oxide with better performance than gate-first. PDA has no prominent effect on the performance of transistor. PPA has been shown to have a passivation effect of certain defects in the oxide and interface. Alternative structures have been studied such as the structure MOSHEMT with lattice matched and pseudomorphic, showing best performances like IdMAX=300mA/mm, gmMAX=200mS/mm, fT=200GHz and fMAX=50GHz for a transistor gate length of 100nm. DC performance is far from the state of the art, while the RF performances are among the best. The perspective of this work is to improve the oxide quality by lowering the thermal budget and also to use promising structures as MOS-COMB (MOS-Thin body structure with barrier layer between the oxide and semiconductor). The MOSFET InAs with high-performance could also be expected by reducing the thermal budget during the fabrication.LILLE1-Bib. Electronique (590099901) / SudocSudocFranceF

Asymmetric InGaAs MOSFETs with InGaAs source and InP drain

Asymmetric In0.53Ga0.47As MOSFETs with different regrown contacts at source (In0.53Ga0.47As) and drain (InP) have been developed. By introducing a wider bandgap material, InP as drain electrode, higher self-gain g(m)/g(d) has been obtained with reduced output conductance g(d) and improved break-down voltage V-bd. For L-g=100nm, a high oscillation frequency f(max)= 270GHz has been obtained using an InP drain

Characterization of Border Traps in III-V MOSFETs Using an RF Transconductance Method

The significant defect-induced increase in transconductance at high frequencies in some III-V MOSFETs is utilized to reveal the spatial distribution and energy profile of traps in the gate dielectric. The frequency response of the border traps is modeled as a distributed RC network inserted in the small signal model. Surface-channel InGaAs MOSFETs with Al2O3/HfO2 high-k gate dielectric are evaluated; especially the effects of inserting an InP cap layer in the gate stack

InP Drain Engineering in Asymmetric InGaAs/InP MOSFETs

The design of the InP drain layer in asymmetric InGaAs/InP MOSFETs has been studied experimentally. The influence of doping and thickness of the InP drain has been carefully measured and compared with the performance with an InGaAs drain, regarding the output conductance, the voltage gain, and the leakage current. It is shown that the introduction of an undoped InP spacer has a profound effect on the transistor characteristics. Finally, the effect of a gate-connected field plate at the InP drain side has also been studied both in dc and RF data

Asymmetric InGaAs/InP MOSFETs With Source/Drain Engineering

We have developed laterally asymmetric In0.53Ga0.47As/InP MOSFETs with different regrown contacts at the source (In0.53Ga0.47As) and the drain (InP). Introducing a wider bandgap material, InP, as the drain electrode, higher voltage gain g(m)/g(d) has been obtained with a reduced output conductance g(d) and improved breakdown voltage V-bd. For L-g = 50 nm, a high oscillation frequency f(max) = 300 GHz has been obtained using an InP drain. A gate-connected field-plate has been introduced, which contributes to the device saturation with better impact ionization/band-to-band tunneling immunity

High Frequency InGaAs MOSFET with Nitride Sidewall Design for Low Power Application

InxGa1-xAs devices have been widely researched for low power high frequency applications due to the outstanding electron mobility and small bandgap of the materials. Regrown source/drain technology is highly appreciated in InGaAs MOSFET, since it is able to reduce the thermal budget induced by ion implantation, as well as reduce the source/drain resistance. However, regrown source/drain technology has problems such as high parasitic capacitance and high electric field at gate edge towards the drain side, which will lead to large drain leakage current and compromise the frequency performance. To alleviate the drain leakage current problem for low power applications and to improve the high frequency performance, a novel Si3N4 sidewall structure was introduced to the InGaAs MOSFET. Device simulation was carried out with different newly proposed sidewall designs. The results showed that both the drain leakage current and the source/drain parasitic capacitance were reduced by applying Si3N4 sidewall together with InP extended layer in InGaAs MOSFET. The simulation results also suggested that the newly created “recessed” sidewall was able to bring about the most frequency favorable characteristic with no current sacrifice